The present invention is related to input/output (I/O) interface circuits for use with complementary-metal-oxide-silicon (CMOS) integrated circuits, and is more particularly related to I/O interface circuits which are formed by interconnecting various elements of a common cell which may be selectively connected to form selected input/output circuits as desired.
With the advent of semiconductor devices having a large number of transistors arranged in various configurations, it has become advantageous to design a number of basic cells having known characteristics which may be arranged as desired to form semiconductor devices. U.S. Pat. No. 4,412,237 issued Oct. 25, 1983 to Matsumura et al. for "Semiconductor Device" discloses a semiconductor device having a large number of basic cells. Each basic cell is comprised of first and second P-channel transistors and first and second N-channel transistors. The basic cells may be connected in a variety of ways to form logic arrays. The basic cells include a small space extending between both sides of the basic cells which, when arranged in an array, includes a field which may be utilized for interconnecting lines.
U.S. Pat. No. 4,161,622 issued July 17, 1979 to Malcolm et al. for "Standardized Digital Logic Chip" discloses standardized large scale integrated arrays of standard logic cells which may be interconnected as desired to implement a large variety of logic circuit designs. The pattern chosen for the layout of the standard logic cells provides very high cell density, very high utility ratios of the available cells by use of power and data interconnects within the cells.
U.S. Pat. No. 4,148,046 issued Apr. 3, 1979 to Hendrickson et al. discloses a field-effect transistor device having a number of unit cells for use in an analog signal switch.
U.S. Pat. No. 3,439,185 issued Apr. 15, 1969 to Gibson for "Logic Circuits Employing Field-Effect Transistors" discloses a logic circuit which employs field-effect transistors that can be made to implement a number of different logic functions in response to different combinations of control voltages applied to the logic circuits.
U.S. Pat. No. 3,588,848 issued June 28, 1971 to Van Beck for "Input-Output Control Circuit For Memory Circuit" discloses a circuit including field-effect transistors for use in a control circuit for MOS memory circuits.